Logic synthesis and verification algorithms

By: Gary D. Hachtel Contributor(s): Fabio Somenzi Material type: Text

TextLanguage: English Publication details: Springer (India), 2006 Description: xxxii, 564pISBN: 0387310045; 8181284836 (Indian Reprint)Subject(s): Integrated circuits - Very large scale integration - Design - Data processing | Logic design - Data processing | Integrated circuits - VerificationDDC classification: 621.395 HAC(LOG)

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Holdings
Item type	Current library	Call number	Materials specified	Copy number	Status	Date due	Barcode	Item holds
Books	Central Library	621.395 HAC(LOG) (Browse shelf(Opens below))		1	Available		4282

Total holds: 0

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Previous	621.392 HAY(COM) Computer architecture and organization	621.392 HAY(COM) Computer architecture and organization	621.395 GER(ALG) Algorithms for VLSI design automation	621.395 HAC(LOG) Logic synthesis and verification algorithms	621.395 HAC(LOG) Logic synthesis and verification algorithms	621.395 KAT(CON) Contemporary logic design	621.395 MAN(DIG) Digital Design	Next

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